Rant on OpenCL on FPGAs From a Point of View of a Software Developer

This is why I haven’t post any ChaiScipt tutorial recently. I’m busy on a project to bring OpenCL into OpenCV on a Cyclone V SoC Development Board.

There are a lot of reports and articles about how FPGAs are so powerful that they can outperform GPUs. And that OpenCL can unleash FPGA’s full performance in a way that every developer do it.

I’m telling you that.  FPGAs are great. They perform really well. However, they are NOT easy to program(from a software developer’s view) and you need a totally different mindset then programming a GPU to optimized code on a FPGA.

 

My FPGA development board running SVM(Its slow because overhead of converting CV data into OpenCL readable form, not caused by FPGA)

First of all. How can OpenCL C, which is a language that is designed to be compiled into machine code run on a FPGA? It is done by converting your OpenCL code into Verilog, then synthesis it to create the binary the FPGA needs.

What’s the problem then? Easy, It takes forever for the synthesiser to run. The following kernel takes a bit more then an hour to compile. Which is forever for the standard of software developing. And the compiler needs more than 3.5G of RAM to run.

__kernel void compute(int hisGramSize, __global float* blockRes, __global float* blocks, __global float* svm)
{
int size = get_global_size(0);
int id = get_global_id(0);

float result = 0.f;
int offset = id*hisGramSize;
for(int i=offset;i<offset+hisGramSize;i++)
result += blocks[i]*svm[i];
blockRes[id] = result;
}

There is no way anyone can rapidly develop and debug OpenCL for a FPGA. Trial and error won’t work here. That’s a down side. Even more, the kernel can only be compiled offline instead of the usual online compiling we do in OpenCL to ensure portability across different CPU/GPUs. 😦

Setting up OpenCL on a FPGA is a bit of pain too. Programming of the FPGA is done by calling a command in the command line. Annoying. Also, as the kernel is compiled offline. If the runtime version is different from the offline compiler used to compile. Everything fails with no warring. Face-palm.

Besides all the above. There are sill one huge downside of a FPGA. You can’t put too much logic into a kernel. Else one or more of the following can happen.

1. The synthesiser gives up
2. No enough space on the FPGA to store all the logics

If the compile passes. You still have the problem that you can’t pack too much compute units on to the FPGA because the total respurce on the FPGA is limited.

Despite these downsides of FPGA. The upsides of FPGAs are that

1. High Performance per Watt(even compared to a GPU)
2. Very high memory through put
3. Can do lots of things in parallel if possible even we only have on Compute Unit

Hacking OpenCL code into OpenCV on a hackathon.